| 000 -LEADER |
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| fixed length control field |
03900cam a22003494a 4500 |
| 001 - CONTROL NUMBER |
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| control field |
16988301 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
CITU |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20201126072653.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
111004s2012 maua b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2011038128 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780123838728 (pbk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
012383872X (pbk.) |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)ocn755102367 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Transcribing agency |
DLC |
| Modifying agency |
YDX |
| -- |
IBA |
| -- |
YDXCP |
| -- |
BWX |
| -- |
CDX |
| -- |
MHB |
| -- |
DLC |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
pcc |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
QA76.9.A73 |
| Item number |
P377 2012 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
004.2/2 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Hennessy, John L. |
| Relator term |
Author |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Computer architecture : |
| Remainder of title |
A quantitative approach / |
| Statement of responsibility, etc. |
John L. Hennessy and David A. Patterson |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
Fifth Edition. |
| 260 10 - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Amsterdam : |
| Name of publisher, distributor, etc. |
Morgan Kaufmann/Elsevier, |
| Date of publication, distribution, etc. |
c2012. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxvii, 493 pages, 325 unnumbered pages : |
| Other physical details |
illustrations ; |
| Dimensions |
24 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (p. r-1-32) and index. |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Fundamentals of quantitative design and analysis --<br/>Memory hierarchy design --<br/>Instruction-level parallelism and its exploitation --<br/>Data-level parallelism in vector, SIMD, and GPU architectures --<br/>Thread-level parallelism --<br/>Warehouse-scale computers to exploit request-level and data-level parallelism --<br/>Instruction set principles --<br/>Review of memory hierarchy --<br/>Pipelining: basic and intermediate concepts --<br/>Online appendices. Storage systems --<br/>Embedded systems --<br/>Interconnection networks --<br/>Vector processors in more depth --<br/>Hardware and software for VLIW and EPIC --<br/>Large-scale multiprocessors and scientific applications --<br/>Computer arithmetic --<br/>Survey of instruction set architectures --<br/>Historical perspectives and references. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
Computer Architecture: A Quantitative Approach explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and other mobile devices. The book became a part of Intel's 2012 recommended reading list for developers, and it covers the revolution of mobile computing. The text also highlights the two most important factors in architecture today: parallelism and memory hierarchy. The six chapters that this book is composed of follow a consistent framework: explanation of the ideas in each chapter; a "crosscutting issues" section, which presents how the concepts covered in one chapter connect with those given in other chapters; a "putting it all together" section that links these concepts by discussing how they are applied in real machine; and detailed examples of misunderstandings and architectural traps commonly encountered by developers and architects. The first chapter of the book includes formulas for energy, static and dynamic power, integrated circuit costs, reliability, and availability. Chapter 2 discusses memory hierarchy and includes discussions about virtual machines, SRAM and DRAM technologies, and new material on Flash memory. The third chapter covers the exploitation of instruction-level parallelism in high-performance processors, superscalar execution, dynamic scheduling and multithreading, followed by an introduction to vector architectures in the fourth chapter. Chapters 5 and 6 describe multicore processors and warehouse-scale computers (WSCs), respectively. This book is an important reference for computer architects, programmers, application developers, compiler and system software developers, computer system designers and application developers. Fully updated fifth edition covers the twin shifts to mobile and cloud computing, with new material, exercises, and case studies.--Publisher website. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Computer architecture. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Patterson, David A. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Asanović, Krste. |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
|---|
| a |
7 |
| b |
cbc |
| c |
orignew |
| d |
1 |
| e |
ecip |
| f |
20 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
BOOK |
| Edition |
2012 |
| Classification part |
004.22 |