Digital systems design using Verilog / (Record no. 51693)

000 -LEADER
fixed length control field 07277nam a22003617a 4500
003 - CONTROL NUMBER IDENTIFIER
control field CITU
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20211022143427.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 140806s2016 at a b 001 0 eng
010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
LC control number 2014947845
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781285051079
040 ## - CATALOGING SOURCE
Original cataloging agency DLC
Language of cataloging eng
Description conventions rda
Transcribing agency DLC
042 ## - AUTHENTICATION CODE
Authentication code pcc
050 00 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7885.7
Item number .R68 2016
100 1# - MAIN ENTRY--PERSONAL NAME
Preferred name for the person Roth, Charles H.,
Dates associated with a name 1932-
Relator term author
245 10 - TITLE STATEMENT
Title Digital systems design using Verilog /
Statement of responsibility, etc Charles H. Roth, Jr., The University of Texas at Austin, Lizy Kurian John, The University of Texas at Austin, Byeong Kil Lee, The University of Texas at San Antonio.
250 ## - EDITION STATEMENT
Edition statement International edition.
264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc Australia ;
-- Boston, MA :
Name of publisher, distributor, etc Cengage Learning,
Date of publication, distribution, etc [2016]
264 #4 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Date of publication, distribution, etc c2016
300 ## - PHYSICAL DESCRIPTION
Extent x, 582 pages :
Other physical details illustrations ;
Dimensions 24 cm
336 ## - CONTENT TYPE
Content type term text
Content type code txt
Source rdacontent
337 ## - MEDIA TYPE
Media type term unmediated
Media type code n
Source rdamedia
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Carrier type code nc
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500 ## - GENERAL NOTE
General note Charles Roth is Professor Emeritus in Electrical and Computer Engineering at the University of Texas at Austin, where he taught Digital Design for more than four decades. He is the author of Fundamentals of Logic Design, which is in its sixth edition, and Digital Systems Design using VHDL, which is in its second edition.<br/><br/>Lizy John is the B. N. Gafford Professor in Electrical and Computer Engineering at the University of Texas at Austin. Dr. John has been teaching and conducting research in computer architecture and digital systems design for almost two decades. She has coauthored DIGITAL SYSTEMS DESIGN USING VHDL and DIGITAL SYSTEMS DESIGN USING VERILOG and has edited several successful books on computer performance evaluation and workload characterization. She is an IEEE Fellow.<br/><br/>Byeong Kil Lee is Assistant Professor in Electrical and Computer Engineering at the University of Texas at San Antonio, teaching digital design and computer architecture. Before joining academia two years ago, he worked for Texas Instruments for five years. He has several years of industry Verilog design experience.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc Includes bibliographical references (pages 564-566) and index.
505 0# - CONTENTS
Formatted contents note 1. REVIEW OF LOGIC DESIGN FUNDAMENTALS.<br/>Combinational Logic. Boolean Algebra and Algebraic Simplification. Karnaugh Maps. Designing with NAND and NOR Gates. Hazards in Combinational Circuits. Flip-Flops and Latches. Mealy Sequential Circuit Design. Design of a Moore Sequential Circuit. Equivalent States and Reduction of State Tables. Sequential Circuit Timing. Tristate Logic and Busses.<br/>2. INTRODUCTION TO VERILOG.<br/>Computer-Aided Design. Hardware Description Languages. Verilog Description of Combinational Circuits. Verilog Modules. Verilog Assignments. Procedural Assignments. Modeling Flip-Flops Using Always Block. Always Blocks Using Event Control Statements. Delays in Verilog. Compilation, Simulation, and Synthesis of Verilog Code. Verilog Data Types and Operators. Simple Synthesis Examples. Verilog Models for Multiplexers. Modeling Registers and Counters Using Verilog Always Statements. Behavioral and Structural Verilog. Constants. Arrays. Loops in Verilog. Testing Verilog Model. A Few Things to Remember.<br/>3. INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES.<br/>Brief Overview of Programmable Logic Devices. Simple Programmable Logic Devices (SPLDs). Complex Programmable Logic Devices (CPLDs). Field-Programmable Gate Arrays (FPGAs).<br/>4. DESIGN EXAMPLES.<br/>BCD to 7-Segment Display Decoder. A BCD Adder. 32-Bit Adders. Traffic Light Controller. State Graphs for Control Circuits. Scoreboard and Controller. Synchronization and Debouncing. A Shift-and-Add Multiplier. Array Multiplier. A Signed Integer/Fraction Multiplier. Keypad Scanner. Binary Dividers.<br/>5. SM CHARTS AND MIRCOPROGRAMMING.<br/>State Machine Charts. Derivation of SM Charts. Realization of SM Charts. Implementation of the Dice Game. Microprogramming. Linked State Machines.<br/>6. DESIGNING WITH FIELD PROGRAMMABLE GATE ARRAYS.<br/>Implementing Functions in FPGAs. Implementing Functions Using Shannon's Decomposition. Carry Chains in FPGAs. Cascade Chains in FPGAs. Examples of Logic Blocks in Commercial FPGAs. Dedicated Memory in FPGAs. Dedicated Multipliers in FPGAs. Cost of Programmability. FPGAs and One-Hot State Assignment. FPGA Capacity: Maximum Gates versus Usable Gates. Design Translation (Synthesis). Mapping, Placement, and Routing.<br/>7. FLOATING-POINT ARITHMETIC.<br/>Representation of Floating-Point Numbers. Floating-Point Multiplication. Floating-Point Addition. Other Floating-Point Operations.<br/>8. ADDITIONAL TOPICS IN VERILOG.<br/>Verilog Functions. Verilog Tasks. Multi-Valued Logic and Signal Resolution. Built-in Primitives. User Defined Primitives. SRAM Model. Model for SRAM Read/Write System. Rise and Fall Delays of Gates. Named Association. Generate Statements. System Functions. Compiler Directives. File I/O Functions. Timing Check.<br/>9. DESIGN OF A RISC MICROPROCESSOR.<br/>The RISC Philosophy. The MIPS ISA. MIPS Instruction Encoding. Implementation of a MIPS Subset. VHDL Model.<br/>10. HARDWARE TESTING AND DESIGN FOR TESTABILITY.<br/>Testing Combinational Logic. Testing Sequential Logic. Scan Testing. Boundary Scan. Built-In Self-Test.
520 ## - SUMMARY, ETC.
Summary, etc DIGITAL SYSTEMS DESIGN USING VERILOG integrates coverage of logic design principles, Verilog as a hardware design language, and FPGA implementation to help electrical and computer engineering students master the process of designing and testing new hardware configurations. A Verilog equivalent of authors Roth and John's previous successful text using VHDL, this practical book presents Verilog constructs side-by-side with hardware, encouraging students to think in terms of desired hardware while writing synthesizable Verilog. Following a review of the basic concepts of logic design, the authors introduce the basics of Verilog using simple combinational circuit examples, followed by models for simple sequential circuits. Subsequent chapters ask readers to tackle more and more complex designs.<br/><br/> The first chapter presents a summary of the fundamentals of digital design to refresh readers' knowledge and prepare them for the rest of the book.<br/> A wide range of important digital design concepts, including Algorithmic State Machine (ASM) charts, micro-programming, one-hot design, design for synthesis, testing, etc., are covered.<br/> Many digital system design examples, ranging in complexity from a simple binary adder to a microprocessor, help readers learn design skills.<br/> Steps in the design flow are clearly illustrated and explained.<br/> Two chapters (Chapters 3 and 6) treat the basics of all programmable logic devices and provide details of synthesis, mapping, and routing to FPGAs.<br/> Materials are presented generically, rather than attached to a specific vendor or product family.<br/> The authors help students develop the design skill of putting together bigger designs from smaller pieces.<br/> A unique chapter on testing presents information on Built In Self-Test (BIST), Boundary Scan testing, and LFSRs.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Verilog (Computer hardware description language)
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Electronic digital computers
General subdivision Circuits
-- Computer-aided design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element System design
General subdivision Data processing.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name John, Lizy Kurian,
Relator term author.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Lee, Byeong Kil,
Relator term author.
942 ## - ADDED ENTRY ELEMENTS
Source of classification or shelving scheme
Item type BOOK
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Permanent Location Current Location Shelving location Date acquired Inventory number Full call number Barcode Date last seen Price effective from Item type
          COLLEGE LIBRARY COLLEGE LIBRARY SUBJECT REFERENCE 2020-10-26 47980 621.392 R7422 2016 CITU-CL-47980 2020-10-26 2020-10-26 BOOK